Indicwiki: 1 revision imported from :alpha:Template:Intel_processor_roadmap

2023-12-14T08:45:25Z

1 revision imported from alpha:Template:Intel_processor_roadmap

← Older revision	Revision as of 14:15, 14 December 2023
(No difference)

alpha>Indicwiki: Created page with "{{Navbox |state={{{state|autocollapse}}} |name=Intel processor roadmap |title=Intel CPU core roadmaps from P6 to Lunar Lake |list1={{Clea..."

2023-05-11T05:55:23Z

Created page with "{{Navbox |state={{{state|autocollapse}}} |name=Intel processor roadmap |title=Intel CPU core roadmaps from P6 to Lunar Lake |list1=<noinclude>{{Clea..."

New page

{{Navbox
|state={{{state|autocollapse}}}
|name=Intel processor roadmap
|title=Intel CPU core roadmaps from [[P6 (microarchitecture)|P6]] to Lunar Lake
|list1=<noinclude>{{Cleanup section
| reason=When from ''Bonnell'' to ''Silvermont'' is [[Tick–tock model#Atom roadmap|just a Tick]] (die shrink) than ''Silvermont'' is part of ''Bonnell'' and not a unique microarchitecture?
| date=October 2019
}}</noinclude>
<table class="wikitable" style="border:none; text-align:center;">
<tr>
<th colspan="2" style="background-color:#E6E6FF">[[Intel Atom|Atom (ULV)]]</th>
<td rowspan="38" style="background-color:white; border:none;"></td>
<th rowspan="2">Feature size</th>
<td rowspan="38" style="background-color:white; border:none;"></td>
<th colspan="2" style="background-color:#E6E6FF">[[X86|x86]]</th>
<td colspan="6" rowspan="7" style="background-color:white; border:none;"></td>
</tr>
<tr>
<th style="background-color:#E6E6FF">[[Microarchitecture|Microarch.]]</th>
<th style="background-color:#E6E6FF">Step</th>
<th style="background-color:#E6E6FF">[[Microarchitecture|Microarch.]]</th>
<th style="background-color:#E6E6FF">Step</th>
</tr>
<tr>
<td colspan="2" rowspan="13"></td>
<th>[[600 nm process|600 nm]]</th>
<td rowspan="12">[[P6 (microarchitecture)|P6]]</td>
<td>[[Pentium Pro]] (133 MHz)</td>
</tr>
<tr>
<th>[[600 nm process|500 nm]]</th>
<td>[[Pentium Pro]] (150 MHz)</td>
</tr>
<tr>
<th rowspan="2">[[350 nm process|350 nm]]</th>
<td>[[Pentium Pro]] (166–200 MHz)</td>
</tr>
<tr>
<td>[[Klamath (microprocessor)|Klamath]]</td>
</tr>
<tr>
<th rowspan="2">[[250 nm process|250 nm]]</th>
<td>[[Deschutes (microprocessor)|Deschutes]]</td>
</tr>
<tr>
<td>[[Katmai (microprocessor)|Katmai]]</td>
<td rowspan="7" style="background-color:white; border:none;"></td>
<th style="background-color:#E6E6FF">[[NetBurst]]</th>
<td colspan="4" rowspan="3" style="background-color:white; border:none;"></td>
</tr>
<tr>
<th>[[180 nm process|180 nm]]</th>
<td>[[Coppermine (microprocessor)|Coppermine]]</td>
<td>[[Pentium 4#Willamette|Willamette]]</td>
</tr>
<tr>
<th rowspan="2">[[130 nm process|130 nm]]</th>
<td>[[Tualatin (microprocessor)|Tualatin]]</td>
<td rowspan="2">[[Pentium 4#Northwood|Northwood]]</td>
</tr>
<tr>
<td>[[Banias (microprocessor)|Banias]]</td>
<td style="background-color:white; border:none;"></td>
<th style="background-color:#E6E6FF">[[Hyper-threading|NetBurst(HT)]]</th>
<td style="background-color:white; border:none;"></td>
<th style="background-color:#E6E6FF">NetBurst([[Multi-core processor|×2]])</th>
</tr>
<tr>
<th rowspan="2">[[90 nm process|90 nm]]</th>
<td rowspan="2">[[Dothan (microprocessor)|Dothan]]</td>
<td>[[Pentium 4#Prescott|Prescott]]</td>
<td style="background-color:white; border:none;">⇨</td>
<td>[[Pentium 4#Prescott 2M (Extreme Edition)|Prescott‑2M]]</td>
<td style="background-color:white; border:none;">⇨</td>
<td>[[Smithfield (microprocessor)|Smithfield]]</td>
</tr>
<tr>
<td><s>[[Tejas and Jayhawk|Tejas]]</s></td>
<td style="background-color:white; border:none;">→</td>
<td>⇩</td>
<td style="background-color:white; border:none;">→</td>
<td><s>[[Tejas and Jayhawk#Design and microarchitecture|Cedarmill (Tejas)]]</s></td>
</tr>
<tr>
<th rowspan="2">[[65 nm process|65 nm]]</th>
<td>[[Yonah (microprocessor)|Yonah]]</td>
<td><s>[[NetBurst#Successor|Nehalem (NetBurst)]]</s></td>
<td style="background-color:white; border:none;"></td>
<td>[[Pentium 4#Cedar Mill|Cedar Mill]]</td>
<td style="background-color:white; border:none;">⇨</td>
<td>[[Presler (microprocessor)|Presler]]</td>
</tr>
<tr>
<td rowspan="2">Core</td>
<td>[[Intel Core (microarchitecture)|Merom]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="text-align:left; background-color:white; border:none;">4 cores on mainstream desktop, [[DDR3]] introduced</td>
</tr>
<tr>
<td rowspan="4">Bonnell</td>
<td rowspan="2">[[Bonnell (microarchitecture)|Bonnell]]</td>
<th rowspan="2">[[45 nm process|45 nm]]</th>
<td>[[Penryn (microarchitecture)|Penryn]]</td>
<td colspan="6" style="background-color:white; border:none;"></td>
</tr>
<tr>
<td rowspan="2">Nehalem</td>
<td>[[Nehalem (microarchitecture)|Nehalem]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="text-align:left; background-color:white; border:none;">[[Hyper-threading|HT]] reintroduced, integrated [[Memory controller|MC]], PCH L3-cache introduced, 256KB L2-cache/core</td>
</tr>
<tr>
<td rowspan="2">[[Saltwell (microarchitecture)|Saltwell]]</td>
<th rowspan="2">[[32 nm process|32 nm]]</th>
<td>[[Westmere (microarchitecture)|Westmere]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="text-align:left; background-color:white; border:none;">Introduced GPU on same package and [[AES-NI|AES-NI]]</td>
</tr>
<tr>
<td rowspan="2">Sandy Bridge</td>
<td>[[Sandy Bridge]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="text-align:left; background-color:white; border:none;">On-die ring bus, no more non-[[UEFI]] motherboards</td>
</tr>
<tr>
<td rowspan="4">Silvermont</td>
<td rowspan="2">[[Silvermont]]</td>
<th rowspan="2">[[22 nm process|22 nm]]</th>
<td>[[Ivy Bridge (microarchitecture)|Ivy Bridge]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white; border:none;"></td>
</tr>
<tr>
<td rowspan="2">Haswell</td>
<td>[[Haswell (microarchitecture)|Haswell]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="text-align:left; background-color:white; border:none;">FIVR</td>
</tr>
<tr>
<td rowspan="2">[[Airmont (microarchitecture)|Airmont]]</td>
<th rowspan="9">[[14 nm process|14 nm]]</th>
<td>[[Broadwell (microarchitecture)|Broadwell]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white; border:none;"></td>
</tr>
<tr>
<td rowspan="7">Skylake</td>
<td>[[Skylake (microarchitecture)|Skylake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="text-align:left; background-color:white; border:none;">[[DDR4]] introduced on mainstream desktop</td>
</tr>
<tr>
<td rowspan="7">Goldmont</td>
<td rowspan="3">[[Goldmont]]</td>
<td>[[Kaby Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white; border:none;"></td>
</tr>
<tr>
<td>[[Coffee Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="text-align:left; background-color:white; border:none;">6 cores on mainstream desktop</td>
</tr>
<tr>
<td>[[Kaby Lake#Amber Lake|Amber Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white; text-align:left; border:none;">Mobile-only</td>
</tr>
<tr>
<td rowspan="4">[[Goldmont Plus]]</td>
<td>[[Whiskey Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white; text-align:left; border:none;">Mobile-only</td>
</tr>
<tr>
<td>[[Coffee Lake]] Refresh</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="text-align:left; background-color:white; border:none;">8 cores on mainstream desktop</td>
</tr>
<tr>
<td>[[Comet Lake (microprocessor)|Comet Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white; text-align:left; border:none;">10 cores on mainstream desktop</td>
</tr>
<tr>
<td>[[Cypress Cove (microarchitecture)|Cypress Cove]]</td>
<td>[[Rocket Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white; border:none; text-align:left;">Backported Sunny Cove microarchitecture for 14nm</td>
</tr>
<tr>
<td rowspan="3">Tremont</td>
<td rowspan="3">[[Tremont (microarchitecture)|Tremont]]</td>
<th rowspan="3">[[10 nm process|10 nm]]</th>
<td>'''Palm Cove'''</td>
<td>[[Cannon Lake (microarchitecture)|Cannon Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="text-align:left; background-color:white; border:none;">Mobile-only</td>
</tr>
<tr>
<td>[[Sunny Cove]]</td>
<td>[[Ice Lake (microprocessor)|Ice Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white; text-align: left; border:none;">512 KB L2-cache/core</td>
</tr>
<tr>
<td>[[Willow Cove]]</td>
<td>[[Tiger Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white; border:none; text-align:left;">[[Intel Xe|Xe]] graphics engine</td>
</tr>
<tr>
<td rowspan="2">Gracemont</td>
<td rowspan="2">[[Gracemont (microarchitecture)|Gracemont]]</td>
<th rowspan="2">[[7 nm process|Intel 7]]</th>
<td>[[Golden Cove]]</td>
<td>[[Alder Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white; border:none; text-align:left;">Hybrid, DDR5, PCIe 5.0</td>
</tr>
<tr>
<td>[[Golden Cove#Raptor Cove|Raptor Cove]]</td>
<td>[[Raptor Lake]]</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white;border:none;"></td>
</tr>
<tr>
<td>Crestmont</td>
<td>Crestmont</td>
<th>[[5 nm process|Intel 4]]</th>
<td>Redwood Cove</td>
<td>''[[Meteor Lake]]''</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white;border:none;"></td>
</tr>
<tr>
<td>Skymont</td>
<td>Skymont</td>
<th>[[2 nm process|Intel 20A]]</th>
<td>Lion Cove</td>
<td>''[[Arrow Lake (microprocessor)|Arrow Lake]]''</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white;border:none;"></td>
</tr>
<tr>
<td>TBA</td>
<td>TBA</td>
<th>[[2 nm process|Intel 18A]]</th>
<td>TBA</td>
<td>''[[Lunar Lake]]''</td>
<td style="text-align:left; background-color:white; border:none;"></td>
<td colspan="6" style="background-color:white;border:none;"></td>
</tr>
<tr>
</table>
<ul style="text-align:left;">
<li><s>Strike-through</s> indicates cancelled processors
<li>'''Bold names''' are microarchitectures
<li>''Italic names'' are future processors
</ul>
}}<noinclude>{{Documentation}}</noinclude>

Template:Intel processor roadmap - Revision history

Indicwiki: 1 revision imported from :alpha:Template:Intel_processor_roadmap

alpha>Indicwiki: Created page with "{{Navbox |state={{{state|autocollapse}}} |name=Intel processor roadmap |title=Intel CPU core roadmaps from P6 to Lunar Lake |list1={{Clea..."